Constraint-Based Verification

Sinopse

Constraint-Based Verification covers an emerging field in functional verification of electronic designs, referred to as the "constraint-based verification."nbsp; The topics are developed in the context of a wide range of dynamic and static verification approaches including simulation, emulation, and formal methods.nbsp; The goal is to show how constraints, or assertions, can be used towards automating the generation of testbenches, resulting in a seamless verification flow.nbsp; Topics such as verification coverage, and connection with assertion based verification, are also covered. The book targets verification engineers as well as researchers. It covers both methodological and technical issues.nbsp; Particular stress is given to the latest advances in functional verification. The research community has witnessed recent growth of interests in constraint-based functional verification.nbsp; Various techniques have been developed.nbsp; They are relatively new, but have reached a level of maturity so that they are appearing in commercial tools such as Vera and System Verilog. nbsp;